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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:16:28 03/24/2011 
-- Design Name: 
-- Module Name:    ir - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ir is
    Port ( ir_clk        : in STD_LOGIC;
           ir_clr        : in STD_LOGIC;
           enable_IR     : in STD_LOGIC;
			  instr_reg_in  : in STD_LOGIC_VECTOR (17 downto 0);
           instr_reg_out : out STD_LOGIC_VECTOR (17 downto 0));
end ir;

architecture Behavioral of ir is
	begin
	process(ir_clk, ir_clr)
	variable ir_val : STD_LOGIC_VECTOR (17 downto 0);
	
		begin
		if rising_edge (ir_clk) then
			if ir_clr = '1' then
				instr_reg_out <= (others => '0'); -- rellena con 0 el std_logic_vector
			if enable_IR = '1' then
				ir_val := instr_reg_in;				
			end if;
			end if;
		end if;
		instr_reg_out <= ir_val;
	end process;
end Behavioral;

